1. Field of the Invention
This invention relates generally to power semiconductor devices and, more particularly, to an insulated gate bipolar transistor (referred to as xe2x80x9cIGBTxe2x80x9d hereinafter).
2. Description of Related Art
Traditionally, IGBTs are known as power semiconductor devices with low losses. IGBTs include those of the so-called trench gate type. These trench-gate IGBTs are becoming more important in industrial applications due to their advantages over old or classical IGBTs of the planar gate type. One important advantage lies in the ability to obtain lower channel resistances by integration of a great number of highly miniaturized or xe2x80x9cmicroxe2x80x9d unit cells on a chip. Another advantage is the ability to obtain low on-voltage characteristics. This is resulted from the absence of any pinch-off otherwise occurring due to unwanted formation of parasitic junction field effect transistors (xe2x80x9cJFETsxe2x80x9d). The trench-gate IGBTs are principally free from the risk of such parasitic JFETs owing to the inherent structures thereof.
A plan view of one prior known trench-gate IGBT is shown in FIG. 15. A cross-sectional view of this IGBT as taken along line I-Ixe2x80x2 is depicted in FIG. 16. A lightly-doped n (nxe2x88x92) type layer 2 is formed on a heavily-doped p (p+) type silicon substrate 1. On a surface of this nxe2x88x92-type layer 2, a p-type base layer 3 is formed by diffusion to a depth of approximately 4 micrometers (xcexcm). Further, an n+-type emitter layer 4 with a depth of about 0.5 xcexcm is selectively diffusion-formed in a surface of the base layer 3.
Trenches 5 are formed to penetrate the emitter layer 4 and the base layer 3 in such a manner that each trench has a width of about 1 xcexcm and a depth of 6 to 7 xcexcm, wherein gate electrodes 6 are buried within these trenches 5. A cathode electrode (emitter electrode) 7 is formed to be in contact with the base layer 3 and the emitter layer 4. An anode electrode (collector electrode) 8 is formed on a back surface of the Si substrate 1.
In this trench-gate IGBT, a plurality of unit cells are arrayed and formed with a surface portion of a region laterally disposed between adjacent ones of the plurality of lines of gate electrodes 6 as a cathode region of each unit cell. In the example of FIG. 15 and FIG. 16, a cathode region width D2 which occupies a width D1 of unit cell is great.
With such prior art IGBT, the carrier distribution at a position Y-Yxe2x80x2 of FIG. 16 at an on-time is as indicated by a broken line in FIG. 19, wherein the carrier density near a cathode (K) side surface is lower than that near an anode (A) side surface. This becomes a bar to reduction of the IGBT""s on-voltage at substantially the same level as thyristors. If it is possible to increase the carrier density near the cathode side surface, then it becomes expectable to achieve a lower on-voltage of the IGBT than ever before.
FIGS. 17 and 18 show an example in which the cathode region width D2 occupying the width D1 of a unit cell is lessened by enlarging the width of each trench, in comparison with the IGBT of FIGS. 15 and 16. With the use of such structure, the passage of a hole current which is injected from the p+-type substrate (anode) 1 into the nxe2x88x92-type layer 2 and then flows on the cathode side in a turn-on event becomes narrowed, resulting in occurrence of accumulation or storage of holes at or near the cathode side surface. The result of this is that the carrier distribution at the Y-Yxe2x80x2 position becomes as indicated by a solid line in FIG. 19: the carrier density near the cathode region surface gets higher. Further, with an increase in this hole density, electron injection takes place from the cathode into the device interior in order to satisfy the carrier neutralization condition. Since an electron current from the cathode to the anode flows in a channel region which is controlled by the gate electrode 6, there is no appreciable resistance increase otherwise occurring due to the narrowing of the cathode region width D2.
As apparent from the foregoing, it is possible to lower the IGBT on-voltage to almost the same level of that of thyristors through optimization of the trench gate width, the cathode region width, and further the trench gate depth and the like. This has already been reported in, for example, U.S. Pat. No. 5,329,142 or IEDM Technical Digest 1993, pp. 679-682. The resultant IGBT with its on-voltage lowered by the use of the above-stated technique is specifically called the carrier injection enhanced gate bipolar transistor (IEGT) in some cases.
As previously stated, widening the trench gate width for achievement of a lower on-voltage would result in occurrence of several disadvantages. For example, in order to bury a polycrystalline silicon (polysilicon) gate electrode in a trench with a width of about 10 xcexcm, a need is felt to deposit a polysilicon which is about 5-xcexcm thick. Thus, the manufacturing or fabrication efficiency decreases. Also note that when such polysilicon is buried in a large volume of trench, large stress is applied to the trench region. This can cause crystal defects at trench edges, which leads to a decrease in reliability and a decrease in production yields due to current leakage or else.
An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching the second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern, a first main electrode in contact with the emitter layers and the base layer, and a second main electrode formed at a bottom surface of the first semiconductor layer.